AMD has launched its second-generation 3D V-Cache technology with the Ryzen 7 9800X3D, featuring a structural redesign. In this new iteration, the SRAM die is positioned underneath the CCD. Notably, the SRAM die is larger than the CCD located above it.
Expert Roman Hartung, known as der8auer, analyzed a defective Ryzen 9 9950X3D using a diamond saw and ion beam cleaning. The process revealed that the cache chip is 5 to 6 micrometers thick, while both dies are ground to under 10 micrometers for assembly.
The connection utilizes hybrid bonding where copper surfaces adhere directly without soldering. Through-Silicon Vias are exposed during grinding to facilitate this link. Non-conductive parts were coated for imaging via a scanning electron microscope.