Samsung unveiled a three-stage High Bandwidth Memory roadmap at Hot Chips 2026, culminating in a new architecture called zHBM. This design merges memory and compute into a vertically integrated package, moving processing tasks directly into the memory system.
The strategy begins by adding control functions to the HBM base die, followed by offloading operations into the logic layer. Samsung has already moved the HBM4 base die to a 4nm logic process to improve power efficiency and reduce the overall physical die area.
While zHBM targets AI and HPC accelerators by stacking DRAM over processors, it faces thermal challenges. Current HBM4 offers 1 to 5 TB/s of bandwidth, but no launch date for zHBM is set, and GDDR remains more economical for standard graphics card applications.