Micron Design Architecture Fellow Raghu Sreeramaneni unveiled HBM4 specifications at Hot Chips 2026, highlighting a bandwidth of 2800 GB/s. The new architecture features 2000 IOs, doubling both the IO count and total channels compared to the HBM3E standard.
The HBM4 design utilizes a base die with a 3D TSV PHY to interface between the host and DRAM stack via point-to-point interposer connections. Micron is also researching stacks beyond 16-Hi, using fusion bonding to achieve single-digit micron pitch resolution.
This advancement addresses a critical bottleneck as compute power grows 3x every two years while memory lags at under 2x. With HBM failures causing 17% of Meta's Llama 3 training interruptions, these architectural improvements are vital for AI reliability.