IBM Unveils Next-Gen Z Chip with Dual Arm ISA

IBM's new 2nm processor natively executes Z and Arm software to support high-performance enterprise workloads and global banking systems.

IBM has unveiled a next-generation Z chip featuring a dual Instruction Set Architecture (ISA) that natively executes both Z and Arm software. Announced by Christian Jacobi at Hot Chips 2026, the 2nm processor features 11 cores running at speeds over 5.7 GHz.

The architecture supports Native z/Architecture and AArch64, allowing KVM virtual machines to run S390X and Arm64 simultaneously. The chip includes a 432 MB virtual L3 cache, a 3.5 GB L4 cache, a dedicated I/O DPU, and hardware accelerators for AI and crypto.

This development is critical as IBM Z and LinuxOne handle 68% of global production IT workloads, including 77 of the top 100 banks. By integrating Arm support into its enterprise hardware, IBM expands the versatility of its upcoming high-performance servers.


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