IBM Unveils Sub-1nm Chip with 0.7nm Architecture

IBM debuts 0.7nm chip technology featuring a 3D nanostack design, offering 50% more performance and 70% better efficiency than 2nm nodes.

On June 25, 2026, IBM unveiled sub-1 nanometer chip technology featuring a 0.7 nm node, also known as the 7 angstrom node. Utilizing a three-dimensional nanostack architecture, the design vertically stacks and staggers nanosheet-based transistors through 3D sequential integration. This breakthrough allows for nearly 100 billion transistors on a fingernail-sized chip, doubling the density of IBM's 2021 2 nm node. Director of IBM Research Jay Gambetta noted the technology offers up to 50 percent more performance and 70 percent greater energy efficiency. Research presented at VLSI 2026 showed 40 percent scaling in SRAM. IBM is developing these processes at its Albany, New York facility using ASML’s High NA EUV lithography tool alongside partners Lam Research, Tokyo Electron, and SCREEN. IBM also announced Anderon, a standalone quantum foundry, with a production path for nanostack tech within five years.