Intel is developing Core Series 3 mobile processors, codenamed Wildcat Lake, derived from the Core Ultra Series 3 Panther Lake family. These chips utilize an organic Multi-Chip-Package measuring 35 x 25 x 1.23 mm, replacing the larger Foveros packaging.
The architecture features an Intel 18A Compute-Die and TSMC N6 platform I/Os linked via Universal Chiplet Interconnect Express. While the I/O die area is reduced by 15%, the UCIe interconnect area is 70% larger than Foveros due to a 110 µm bump pitch.
This series targets efficiency with a 64-bit DRAM interface and 6-layer PCB. Connectivity includes two Thunderbolt ports, WiFi7, and 6x Gen4 PCIe lanes. However, camera PHYs are removed, and audio components are scaled back to three DSPs and 3.0 MB memory.