Intel unveiled its Diamond Rapids processor at Hot Chips 2026, featuring 256 cores across 16 CPU tiles. Built on the Intel 18A-P process, the chip utilizes a 4x4 layout of 16-core dies. The architecture lacks SMT but supports AMX and AVX 10.2 instructions.
The design incorporates four Intel 3-T cache-base tiles, optimized for Through-Silicon Vias. Each base tile houses 320MB of L3 cache wired to 64 cores, totaling 1.28GB of Last Level Cache. Two Fabric Hub I/O tiles manage the integrated memory controllers.
Scheduled for a 2027 release on a new platform, Diamond Rapids uses UCIe-S for chip-to-chip connectivity. This modular approach marks a significant shift in Intel's data center strategy, prioritizing high-density cache and advanced manufacturing nodes.