Tensordyne Tape-Outs 138B Transistor AI Chip

Tensordyne unveils the TDN-AIP chip, using logarithmic math to slash power consumption for AI inferencing and agentic workloads.

Tensordyne has achieved tape-out for its TDN-AIP chip on TSMC's N3P process, featuring 138 billion transistors and 144 GB of HBM3E memory. The 16-core chip utilizes a 300W TDP and LNS8 logarithmic mathematics to replace multiplications with additions, supporting NVFP4, FP8, and FP16 formats. Rather than individual accelerators, Tensordyne offers rack-scale solutions codenamed Napier. A single TDN72 pod containing 72 chips consumes one-fifth the power of an NVIDIA Grace-Blackwell-NVL72. A full 120 kW air-cooled rack delivers 608 PFLOPS and 42 TB of HBM3E. Hardware units start with a 3,000W Compute Tray housing nine chips, 8 TB of SSD storage, and a Xeon host. Developed with Broadcom, HPE, and Juniper, the first chips are expected in labs by late 2026, with full system availability in mid-2027. Tensordyne projects 350 racks can deliver 1 billion tokens per second using 30 MW.