TSMC N2 Node Tape-Outs Quadruple N3 Levels

TSMC's 2nm N2 node achieves 4x tape-outs over N3, featuring GAA nanosheet transistors and significant power efficiency gains.

TSMC Senior Vice President Kevin Zhang announced that the company's N2 node has reached four times the tape-outs of the 3 nm N3 node. Utilizing gate-all-around FET nanosheet transistors, the N2 node provides a 15% performance increase or a 30% power reduction at equivalent levels, alongside a 15% boost in transistor density. High-volume production began in Q4 2025. By July 2026, N2 contributed 3% of revenue, trailing the 5 nm and 3 nm nodes at 33% and 30% respectively. Major customers include Apple for A20 Pro chips and AMD for EPYC Venice server CPUs. TSMC's roadmap includes the N2P variant in the second half of 2026, the N2X in 2027, and the N2U in 2028.